ekiwi Goto Github PK

pain-ter

Upstream: https://github.com/salkinium/upainter. Excursion into the world of 2D graphics rendering on µ-controllers and simulation in Qt.

parsers

educational LL(1) parser generation code

paso

A Chisel Integrated Specification and Verification Language.

patron

work in progress, playing around with btor2 in rust

picojava2-archive

PicoJava2 RTL sources which are published under the Sun Community Source License, which is NOT a Open Source license.

pixy

pixy CMUcam5

pyfirrtl

Generating FIRRTL from Python. Highly experimental. Do not use.

pynq

PYNQ with Chisel and Rust

python-compiler

Some helpful pluming for writing (DSL) compilers in python.

radare2

unix-like reverse engineering framework and commandline tools

radare2-regressions

Regression Tests for the Radare2 Reverse Engineer's Debugger

radare2book

r1 book transcription to r2

regext

Register Extracter

rfuzz

rfuzz: coverage-directed fuzzing for RTL research platform

rfuzz-results

put your out folders here!

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

riscv-sodor

educational microarchitectures for risc-v isa

riscv-softcore-2018

Verilog sources from the RISCV Softcore Contest: https://riscv.org/2018/12/risc-v-softcpu-contest-highlights

rocket-chip

Rocket Chip Generator

rocket-chip-formal

Chisel formal tests applied to rocket chip.

rtl-fuzz-lab

A Modular Open-Source Hardware Fuzzing Framework

rust-playground

just playing around with a new language

schaltungstechnik-spice

ltspice simulations for the introductory circuit design class at RWTH Aachen University

serv

SERV - The SErial RISC-V CPU

serv-chisel

reimplementation of the serv core in Chisel (https://github.com/olofk/serv)

sifive-blocks

Common RTL blocks used in SiFive's projects

simulator-independent-coverage

Project Repo for the Simulator Independent Coverage Research

smup

Simple Microcontroller over Uart to Python communication

sorta

playing around with MS prose

spec-impl