Comments (7)
Sorry @nalzok for the delay, a tinyfpga_bx target has been added with 7c6df67. The iCE40 is too small for the default VexRiscv CPU, but you can build a SERV based SoC with: ./tinyfpga_bx.py --cpu-type=serv --build
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Sorry, it's possible to use VexRiscv but not with the standard variant that is too large for the iCE40 (and would also be with Murax SoC). But you can use the Lite variant of Vexriscv: ./tinyfpga_bx.py --cpu-type=vexriscv --cpu-variant=lite --build
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I tried to start documenting some of this stuff at https://github.com/enjoy-digital/litex/wiki/Soft-CPU
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Thanks for the great work! I will check it out when I can get my hands on my TinyFPGA BX.
The iCE40 is too small for the default VexRiscv CPU
I see... Would it take a lot of effort to use Murax SOC instead?
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(and would also be with Murax SoC)
I'm a little surprised to learn this. ICESugar, an iCE40UP5K-powered development board, is able to run Murax SOC (link in Chinese), and I can confirm that since I also own that board. TinyFPGA BX has 8K logic elements, so I would expect it to do more. I'll do some investigation once I have some free time...
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@nalzok - The VexRISCV definitely fits on the iCE40UP5K and the TinyFPGA BX. You just have to disable things like the hard multiplier and divider which is what the lite
variant does.
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Got it! Thanks @mithro for the explanation. Feel free to close the issue if you have nothing to add! @enjoy-digital
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