Changsong Li's Projects
AMBA bus lecture material
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
A softcore processor with ARM9TDMI architecture
FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method
git clone of http://code.google.com/p/axi-bfm/
Bypass domain, CIDR list. Block domain list.
Some knowledge about CRC.
GreenLib official mirror, please use git.greensocs.com for issues and contributions
HDL libraries and projects
Implement of CIC Filter base on Hogenauer's Paper.
RTL, Cmodel, and testbench for NVDLA
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Icarus Verilog
Micro-ARchitectural Full System Simulator for RISC-V
SystemC/C++ library of commonly-used hardware functions and components for HLS.
Some study case of Altera NIOS core
GPGPU microprocessor architecture
Open source IP collection
OpenTitan: Open source silicon root of trust
PicoRV32 - A Size-Optimized RISC-V CPU
Config files for my GitHub profile.
Some code for prbs
An open-source microcontroller system based on RISC-V
Reed Solomon encode and decode algorithm research.