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32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

571941920.github.io

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

blogbackup

cplusplusthings

C++那些事

digital-signal-processing-codes

This is a repository where I added my DSP codes that have written in Matlab (without built-in function). I have also commented inside every code so that it will become helpful for newbies. Also added cross-check using Library Function.

dump1090_sdrplus

Dump1090_sdrplus is a Mode S decoder for Software Defined Radio (SDR) devices including RTL SDR, HackRF, Airspy and SDRplay.

esp-idf

Espressif IoT Development Framework. Official development framework for ESP32.

fft

fpga-application-development-and-simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

gnuradio

GNU Radio – the Free and Open Software Radio Ecosystem

gr-grnet

GNURadio TCP/UDP source and sink blocks rewritten in C++/Boost. UDP block has header/crc options available as well.

gr-ieee802-11

IEEE 802.11 a/g/p Transceiver

gr-tutorial

A tutorial OOT module for GNU Radio

graduation-project-equ

OFDM channel estimation and equalization

hellogithub

:octocat: 分享 GitHub 上有趣、入门级的开源项目

hexo-helper-live2d

Add the Sseexxyyy live2d to your hexo!

hexo-theme-claudia

📌 Concisely designed & easy to config, match device dark mode, 90+ Lighthouse scoring

iir-bandstop-filter

Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic

insightface

Face Analysis Project on MXNet and PyTorch

iq_imbalance-compensation

p4924

python

All Algorithms implemented in Python

simplenes

An NES emulator in C++

wireless-communication-exam

Estimation and correction of IQ imbalance in a QPSK modulation

xilinx-fpga-pcie-xdma-tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核