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Cheng's Projects

aes icon aes

AES encryptor/decryptor realisation (CBC)

aes-1 icon aes-1

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes-128 icon aes-128

Single pipeline AES 128 bit encryption using S-box as Look up table.

aes-cipher-chip icon aes-cipher-chip

An AES cipher chip supporting 128/256 ECB mode with 8-bit half-duplex data bus, being taped out using SMIC 130nm process.

arbiter-puf icon arbiter-puf

Arbiter-based Physically Unclonable Function (PUF) is one kind of the delay-based PUFs that use the time difference of two delay-line signals.

cbc icon cbc

CBC block cipher mode of operation for AES.

cmac icon cmac

Implementation of the CMAC keyed hash function using AES as block cipher.

gcm icon gcm

Galois Couter Mode implementation in Verilog.

gcm-aes icon gcm-aes

Galois Counter Mode Advanced Encryption Standard GCM-AES

hello-universe icon hello-universe

I don't know what is this,but I create it finally,ahahahaha

limbo icon limbo

Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

openmpl icon openmpl

An open multiple patterning framework

reggenperl icon reggenperl

Generate Regisiter Verilog/Excel From a Description File

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