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2-core-mips-r10k-processor

2-core MIPS R10K style OoO Processor with Snooping MSI and Pipeline Bus

470-2waysmt

Two-way superscalar out-of-order processor with simultaneous multi-threading

470_r10k2way

r10k for 470

470panda

Automatically exported from code.google.com/p/470panda

back40computing

Automatically exported from code.google.com/p/back40computing

conte-lake

A 32-bit RISC processor built in Verilog for CS 3220 Spring 2017

convdbn

convey

Convey MX-100

deep-learning-course

desktop_parallelism_analysis_2018

Testbench description and experimental results for parallelism study in state-of-the-art desktop systems.

double-buffered-reorder-fifo

A parameterized number of data words are written into a reorder memory and then popped out in order when memory is full.

dual-issue-pipelined-multimedia-processor-architecture-

Developed a Dual-issue Pipelined Multimedia Processor based on SONY Cell SIMD ISA with 2 block direct mapped cache. • The functional design was created in System Verilog and parser script in PERL that converts Assembly language to 32 bit of instructions. • Successfully detected and resolved all the hazards like Data Hazards (RAW & WAW), Structural Hazards and Control hazards

ee470_blackparrot

eecs470_proj4

embedded_interview

This is the repo for Embedded engineer to prepare their interview

flux-documentation

Everything you need to get started with flux for EECS 470

interview

Everything you need to prepare for your technical interview

interview-1

Interview questions

mips32-cpu

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

nlp_hw2

hw2

oops

OoOPs - Out-of-Order MIPS (TM) Processor

pasc

Parallel Array of Simple Cores. Multicore processor.

processor-uvm-verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

rekcarc-tsc-uht

清华大学计算机系课程攻略 Guidance for courses in Department of Computer Science and Technology, Tsinghua University

reorder-buffer-4-way-o3-cpu-verilog

ReOrder buffer implementation for superscalar out of order CPU

riscy-ooo

RiscyOO: RISC-V Out-of-Order Processor

riscyoo_design_doc

Design document for RiscyOO processor

scoreboarding-computer-architecture-in-python

Implementation of Scoreboarding, a technique for dynamically scheduling a pipeline so that the instructions can execute out of order when there are no conflicts and the hardware is available, in python

seniordesignproject

Register Rename and Branch Prediction modules for a 2 way superscalar, out of order computer processor

special-purpose-processor

This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)