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Abhishek Jain's Projects

cask icon cask

Generate and tune custom architectures for sparse linear algebra

ccf icon ccf

CGRA Compilation Framework

colmajor-spmv-backend icon colmajor-spmv-backend

Source code that accompanies the paper "An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators"

daco icon daco

Dataflow Coprocessor Overlay for FPGAs

dynaburst icon dynaburst

An evolution of our multi-banked nonblocking cache that uses bursts to extract additional bandwidth from DRAM when access patterns are short and irregular.

gemm_hls icon gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

gemx icon gemx

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

hisparse icon hisparse

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

hls4ml icon hls4ml

Machine learning in FPGAs using HLS

hls_tutorial_examples icon hls_tutorial_examples

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

hlslib icon hlslib

A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

idea icon idea

iDEA FPGA Soft Processor

maeri icon maeri

MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)

matchlib icon matchlib

SystemC/C++ library of commonly-used hardware functions and components for HLS.

mshr-rich icon mshr-rich

A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns.

plasticinetutorial icon plasticinetutorial

This repository contains tutorial material for building applications in pytorch and networkx, and targeting the Stanford Plasticine accelerator.

python-graph icon python-graph

Automatically exported from code.google.com/p/python-graph

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