alexmontgomerie Goto Github PK

4nec2_helical_gen

source code to generate .nec files for helical wire antennas

alexmontgomerie

axis_sink

bluespecintroguide

An introductory guide to Bluespec (BSV)

braille_boys

project files

cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

collabo-landing-page

A landing page outlining Collabo's goals and features

collabo_test

deeplearning

def

DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators

drampower

Fast and accurate DRAM power and energy estimation tool

dsam

Scripts to obtain bit-level switching activity of CNNs. Requires Caffe.

dsd_v2

embeddedsystems-eie3

Embedded systems course at Imperial College London 2018

extendedbitplanecompression

Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.

fccm-demo

finn

Dataflow compiler for QNN inference on FPGAs

fpgaconvnet-hls

fpgaconvnet-model

Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.

fpgaconvnet-optimiser

Optimiser for mapping convolutional neural network models to FPGA platforms.

fpgaconvnet-tutorial

A collection of tutorials for the fpgaConvNet framework.

fpgaconvnet-website

The work done at the Intelligent Digital Systems Lab at Imperial College London aims to address this demand with fpgaConvNet: a toolflow for designing Convolutional Neural Network (CNN) accelerators for FPGAs with state-of-the-art performance and efficiency.

graffitist

Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlow.

hpce-2018-cw1

huffman-chisel

A Chisel implementation of Huffman coding for a static code table

memory_io_unit

ml

pommel

Analysing power consumption of the memory subsystem for machine learning applications

portfolio

My online portfolio

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf