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Name: Aly Elruby
Type: User
Bio: Digital IC Design & Verification ENG
Name: Aly Elruby
Type: User
Bio: Digital IC Design & Verification ENG
RTL code via verilog to design Asyn. FIFO and it's testbench
3x3 Matrix inversion
RV64IMAC modelling using System Verilog HDL
Sequential-8x8-multiplier RTL code using verilog
simple uvm environment to test ALU
N x N matrix multiplication using systolic array approach written in HDL language
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