Related Issues (20)
- Make `Module` explode if you try to modify it after it's elaborated
- Extremely slow Verilog generation HOT 5
- Constraint generation from platform resource with `DiffPairs` of type LVDS incorrect. HOT 1
- Adding simulator processes after starting the simulation is not well-defined HOT 2
- Indexing into signals with layouts could be improved HOT 1
- `AttributeError` caused by `UnusedElaboratable` after an elaboratable has failed its initialization HOT 1
- `create_missing_domain` uses `platform.request()` in deprecated mode in all platforms
- Views with an array layout should have `len()` applicable to them
- `stream.Signature` should allow setting the init value for the payload HOT 4
- Views with an array layout should be indexable with a slice HOT 1
- VCD files do not display glitches and can get extremely confusing HOT 2
- Unshaped enumeration values don't work when used in a constant initializer
- Allow comparison of `data.Const` with `dict` and `list`
- Warn after simulation ends if a domain's clock isn't driven by either logic or testbench
- Add a way to have fine grained control over `oe` for `io.Buffer`, `io.FFBuffer`, `io.DDRBuffer` HOT 2
- Add a `PortLike` that can be used in simulation to test designs which instantiate I/O buffers HOT 2
- View of ArrayLayout cannot be indexed with a negative `int` HOT 2
- Allow accessing argument-less predicates on enum views without defining a custom view class HOT 1
- Improve diagnostics on module.domain/module.domains mixup HOT 1
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