amirajnigam Goto Github PK

automation_with_python

c_coding_challenge_100days

data_structure_and_algorithms

embedded_faq

Good Embedded Systems interview questions

forward_error_correction_5g_ee277a

SJSU EE277A Forward Error Correction Code(Polar and Turbo) Implementation on emulated x86 and ARM A9 processor.

freertos_game_development_cmpe244

Bubble shooter is an arcade game that has bubbles or balls present on the screen. The bubbles are of different colors and the goal is to clear them by forming a group of bubbles (3 or more) of the same color. Points are earned upon clearing the bubbles and increases with the number of bubbles cleared in a single shot. The player wins upon clearing the screen and loses when the bubbles touch the bottom of the screen.

mips_isa_dot_product_ee275

The aim of this project is to design a Python code to implement forward chaining in the design. This model will showcase how using the Forward Chaining methodology could enhance the effectiveness of the design. This technique utilizes the potential of the hardware Architecture to its maximum to give optimum speed and better time management as an output. A major effect of pipelining is to change the relative timing of instructions by overlapping their execution. This introduces data and control hazards. Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on the unpipelined machine. The MIPS architecture often faces various hazards: Structural Hazard, Data Hazard, Control Hazards. These hazards may introduce a stall in the architectural pipeline. Stalls could be due to cache miss or hazards in the pipeline. These stalls are good to avoid a hazard but do not serve the purpose of pipelining which is to increase the throughput of the design. Operand forwarding is a technique to get optimized design by controlling the hazards and preventing stalls in the different cycles of pipelining. The idea behind forwarding is simple: if a register $r has not yet been updated with its ”new value” by the time a later instruction needs the value of $r, the data can be forwarded if it is available at or before the time it is needed. This involves extra hardware in the form of wires, hazard-detection, additional MUXes, etc. This paper provides a simple example of enabling forward chaining in the structure to prevent pipelining hazards and stalls in different clock cycles/stages. We recognize this by analyzing a simple code in python that functions without forward chaining then we will modify this code to run with faster speed by introducing forward chaining to it. This new process will be gauged by watching the CPU performance during run-time and execution of both the design codes.

practice_code

rc_car

RC Car Development Project

smart-cane

Smart Cane is designed to help persons with visual impairment. The can help person detect itself by beeping and warn the user when the person nears an obstacle. It also sends an emergency text if the cane falls and is not picked back up within some time.

spi_bit_banging

Bit banging is a technique for serial communication in which the whole communication process is handled via software instead of dedicated hardware.

stepper_motor_control_ee242

Designed prototype system using Raspberry Pi, PWM motor drive, NEMA stepper motor, LSM303 sensor and an ADC module with a potentiometer. Additionally, to operate this prototype system by changing the output to the ADC input through potentiometer. The stepper motor will operate at different duty cycle and the stepper motor rotation is recognized and recorded by LSM303 accelerometer and Magnetometer. Implementation of FFT to perform validation of data and efficiency is calculated through power spectrum analysis. Verification is done through Nyquist criteria Fs>= 2Fm.

stm32f446re_drivers

STM32 Nucleo F446RE onboard peripheral controller drivers for GPIO, SPI, I2C, UART peripherals.

tcp_http_operation_ciscopacketracer_ee281

Implement Routing Information protocol and tested Layer 2 and Layer 3 devices interfacing within a network and configured the Spanning Tree protocol in Cisco Packet Tracer.

two_state_16bit_pipelined_adder_ee275

16- bit Adder in Verilog(VerIDE)