andy89926 Goto Github PK
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andy89926's Projects
accdnn
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
basic_verilog
Must-have verilog systemverilog modules
nutshell
RISC-V SoC designed by students in UCAS
riscv-linux
RISC-V Linux Port
rocket-chip
Rocket Chip Generator
vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
xjtu-tripler
This repository is the backup of XJTU-Tripler project, participating dac19 system design contest
zju-ncov-hitcarder-sample
Sample of https://github.com/Long0x0/ZJU-nCov-Hitcarder.
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