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accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

autosa

AutoSA: Polyhedral-Based Systolic Array Compiler

awesome-cv

Awesome CV is LaTeX template for your outstanding job application

billm

BiLLM: Pushing the Limit of Post-Training Quantization for LLMs

binaryvit

BinaryViT: Pushing Binary Vision Transformers Towards Convolutional Models

building-accelerated-applications-with-vitis

Support material for the Building Accelerated Applications with Vitis webinar series

chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

cnn-using-hls

Convolutional Neural Network Using High Level Synthesis

co-ml-papers

The repository archives papers regarding the combination of combinatorial optimization and machine learning and corresponding reading notes.

csci_596_final_project

CSCI 596 Final Project

deepeda

dmazerunner

dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators

finn

Dataflow compiler for QNN inference on FPGAs

flexcnn

fpgaconvnetmaxeler

Running streaming-based Convolutional Neural Networks on maxeler DFE devices

fracbnn

ftdnn

FPGA-tailored DNN

gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

gemmini

Berkeley's Systolic Array Generator

grain-tracking-algorithm-based-on-highly-parallel-dbscan

hisparse

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

hls_tutorials

Tutorials on HLS Design

hlslib

A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

incubator-tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

interstellar-cnn-scheduler

Tool for optimize CNN blocking

itc99-poli

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino (I99T)

logicregression

lpcv2021_winner_solution

lutnet

memtorch

A Simulation Framework for Memristive Deep Learning Systems