Name: Alireza Khadem
Type: User
Company: University of Michigan
Bio: Graduate student from the EECS Department of the University of Michigan
Location: Ann Arbor, MI, USA
Blog: Arkhadem.com
Alireza Khadem's Projects
Config files for my GitHub profile.
COmputation Reuse-aware Neural network accelerator
Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA 2019 paper "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability". Paper is at: https://people.inf.ethz.ch/omutlu/pub/CROW-DRAM-substrate-for-performance-energy-reliability_isca19.pdf.
Fast and accurate DRAM power and energy estimation tool
Graph Constitutional Network C implementation
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Swan Benchmark Suite
High-efficiency floating-point neural network inference operators for mobile, server, and Web