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avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

avsdpll_3v3

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

avsdpll_3v3-1

Analog IP of On-chip clock multiplier (PLL) using the OSU 180nm technology

data-structures-and-algorithms

Data Structures and Algorithms in Python

fault

A complete Open Source Design for Testing (DFT) Solution

gitgithubmasterclass

First repository

gitgithubmasterlcass

First repository of the LPA's Git and GitHub Masterclass

gitignore

A collection of useful .gitignore templates

hangman

html5-boilerplate

A professional front-end template for building fast, robust, and adaptable web apps or sites.

icc2_workshop_collaterals

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings

mypy

Optional static typing for Python 3 and 2 (PEP 484)

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane-workshop

openlane_build_script

This script builds openlane and all its dependencies on an Ubuntu (only) System.

openlane_sky130

repository for openlane workshop

password_generator

physical-design

Physical Design Flow from RTL to GDS using Opensource tools.

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

python_challenge

raven-picorv32

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

risc-v-core-1

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

risc-v-cpu-core-using-tl-verilog

risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom

risc-v_core_4_stage

riscv_myth_workshop_dec20-ShonTaware created by GitHub Classroom

risc-v_myth_workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop

rock-paper-scissor

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

tensorflow-deep-learning

All course materials for the Zero to Mastery Deep Learning with TensorFlow course.

tip-calculator