audiy Goto Github PK

An FPGA&CPLD engineer in a certain circuit design department. What a pretty circuit!
Twitter: @AUDIY14
GitHub: AUDIY

1. FIR_x2
   FPGA based PCM oversampling FIR filter (oversample ratio: 2).
2. AUDIY_Verilog_IP
   Verilog IP that AUDIY originally designed.
3. AUDIY_OSPCB
   Open Source PCB Files Engineered by AUDIY.
4. DSFIO
   DSD Stream File (*.dsf) reader library written in C.

電子回路わからん日記 (https://audio-diy.hatenablog.com/)

1. 第15回ACRiウェビナー：X界隈のFPGAエンジニア集合！
   Theme: Efinix Trionを使って嵌ったこと

1. FPGA
2. Verilog HDL
3. Python
4. C/C++
5. Audio Signal Processing
6. Electronic Circuit Design

1. C++
2. SystemVerilog (including SVA)
3. VHDL
4. PSL assertion