Comments (1)
TODO:
- A graph displaying the bounds and utilization portions in the bottom-up column. Divide accordingly (per distribution / per buckets size)
Zipf 128
- typically core bound
- no actual memory bounds
- low cache bound (under 2% for each cache level)
One metric recorded poor Port Utilization, indicating stalls in the so called Back-End of the processor where an out-of-order scheduler dispatches ready microoperations to their respective execution units. The assumption is that either there are dependencies in the data that need to be fulfilled in order for certain micro-ops to be dispatched, or certain ports are being overloaded with a high amount of data. A desired strategy for the latter is vectoring the code to reduce the pressure on such ports.
from thesis.
Related Issues (20)
- AGMS VTune Memory Access Analysis
- Fast-AGMS VTune Memory Access Analysis
- AGMS VTune Microarchitecture Exploration Analysis
- Memory Tuning AGMS
- Memory Tuning Fast-AGMS
- Benchmark AGMS Optimized
- Benchmark Fast-AGMS Optimized
- Visualization Ideas
- Related Work
- Vectorization and AVX Research
- Questions to Martin HOT 14
- Implement H3 Bucket Hashing Function HOT 2
- TODO
- SIMD Notes
- Questions For Martin HOT 1
- Writing Ideas/Notes
- Microarchitecture Exploration Notes
- Hotspots Notes HOT 3
- Writing TODO
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from thesis.