Comments (3)
And Scott promised to have this signal an error unless somebody uses the parameter i_know_this_is_usually_a_bad_idea_p.
M
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Attempted fix in PR #39
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PR #39 accepted and merged.
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Related Issues (20)
- Hardcoded address width in bsg_cache_to_dram_ctrl HOT 1
- Should have comment explaining when to use scan here
- long term change
- Add comment that describes difference between this SIPO and others HOT 1
- Questions regarding getting to high frequency on bsg_link/bsg_comm_link HOT 4
- Document on how to add and simulate PLL to bsg_chip
- DT and RT getting stuck sometimes HOT 4
- Problem with testing on `bsg_dataflow` modules
- Undefined parameter used when instantiating bsg_mem_1rw_sync HOT 1
- Syntax errors in generated hard-macro-swapping verilog files when using Python3 HOT 2
- bsg_cache optimization -- don't replay TL instruction if there is no TL instruction HOT 4
- :bug: sync_len_lp is undeclared and undefined in config_snooper.v HOT 2
- bsg_comm_link_master_calib_skip_rom.v is broken HOT 1
- bsg_cache.v ready_o may be yumi_o HOT 2
- Add code for FPGA side of bsg_link HOT 2
- How can we use a basejump_stl component as a top-level module? HOT 9
- bsg_cache_to_test_dram does not support multiple outstanding reads per channel HOT 1
- bsg_nonsynth_dramsim3 failing testbench
- Broken cache testbenches HOT 5
- Release bsg_link FPGA implementation
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