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ai-crash-course

AI-Crash-Course, published by Packt

avmm_sha3

UVM testbench for an sha3 implementation with Avalon MM interface

avst_adder

Example setup for UVM driven Icarus Verilog Simulation

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

axi4lite_sha3

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

caravel_user_project

https://caravel-user-project.readthedocs.io

deploying_cnn_on_fpga_using_opencl

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

hdl

ibm_watson_trials

labguides

Labs for SDR for Engineers textbook

lecturematerials

Slides and other materials for lectures related to SDR for Engineer textbook

low-power-design-vsd-workshop

Low Power Design Workshop By Srikanth Jadcherla and VLSI Systems Design

lowpower

Various low power labs using sky130

meta-avnet

Used for overriding files generated by PetaLinux with Avnet board specific configurations.

opentitan

OpenTitan: Open source silicon root of trust

petalinux

Repository used to support automated builds under PetaLinux tools that use Yocto.

phasedarray

10 GHz Phased Array beamforming labs

pipecnn

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

r-fpga-challenge

⚡⚡Weekly FPGA coding challenges ⚡⚡

rsyocto

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

rt

A Full Hardware Real-Time Ray-Tracer

thinkdsp

Think DSP: Digital Signal Processing in Python, by Allen B. Downey.

tinytpu

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

vitis

Vitis Repository for Avnet Designs

woset-workshop.github.io

Workshop on Open-Source EDA Technology (WOSET)