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Comments (6)

garywangcn avatar garywangcn commented on August 16, 2024

Thanks frank.

The GPIO is supported in current code(dts), but the uart0,1 and 3 are not added in dts, if we need them, please add the following lines to mt7623.dtsi and rebuild the kernel.

uart0: serial@11002000 {
	compatible = "mediatek,mt7623-uart",
		     "mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART0_SEL>,
		 <&pericfg CLK_PERI_UART0>;
	clock-names = "baud", "bus";
	status = "disabled";
};

uart1: serial@11003000 {
	compatible = "mediatek,mt7623-uart",
		     "mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART1_SEL>,
		 <&pericfg CLK_PERI_UART1>;
	clock-names = "baud", "bus";
	status = "disabled";
};

uart3: serial@11005000 {
	compatible = "mediatek,mt7623-uart",
		     "mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART3_SEL>,
		 <&pericfg CLK_PERI_UART3>;
	clock-names = "baud", "bus";
	status = "disabled";
};

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garywangcn avatar garywangcn commented on August 16, 2024

I'd like to close this ticket, is it okay? @frank-w

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frank-w avatar frank-w commented on August 16, 2024

I'd like to enanle at least 1 uart additionally to log-port. Are there Problems if it's enabled?
are the other gpio working?

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garywangcn avatar garywangcn commented on August 16, 2024

All GPIO-s are working fine, there is a script to control GPIO:
SYS_FILE=/sys/devices/platform/1000b000.pinctrl/mt_gpio

mt_gpio_mode()
{
pin=$1
mode=$2

if [ ! -f ${SYS_FILE} ]; then
exit 1
fi

echo "mode $pin $mode" &gt; ${SYS_FILE}

return 0
}

mt_gpio_dir()
{
pin=$1
dir=$2

if [ "x${dir}" == "xout" ]; then
dir_val=1
else
dir_val=0
fi

if [ ! -f ${SYS_FILE} ]; then
exit 1
fi

echo "dir $pin $dir_val" &gt; ${SYS_FILE}

return 0
}

mt_gpio_out()
{
pin=$1
out=$2

if [ ! -f ${SYS_FILE} ]; then
exit 1
fi

echo "out $pin $out" &gt; ${SYS_FILE}

return 0
}

mt_gpio_in()
{
pin=$1

if [ ! -f ${SYS_FILE} ]; then
exit 1
fi

echo "start $1" &gt; ${SYS_FILE}
result=cat ${SYS_FILE} | grep "$1"

if [ "x${result}" == "x" ]; then
echo "can't get $pin status"
exit 2
fi

pin_val=echo ${result} | awk -F ' |-' '{print $5}'
if [ ${pin_val} == "0" ] ; then
return 0
else
return 1
fi

return 0

}

For GPIO22/GPIO23/GPIO24, we need to set EINTx_BOND_DIS to 1.

image

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frank-w avatar frank-w commented on August 16, 2024

Thx for the info,hoping wiringpi will be ported too
is there any Problem,when enabling uart0/1/3?
In your dtsi-code it seems that every uart need 1 SPI-port. On https://bananapi.gitbooks.io/banana-pi-bpi-r2-open-source-smart-router/content/bpi-r2-gpio-pin-define.html i see only 1 uart (which is it) not affecting any other protocol

Regards frank

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frank-w avatar frank-w commented on August 16, 2024

looked in shematics (page 19)...Uart1 seems to be the gpio-uart (pin 8+10), uart0 is pin 11+13 ( gpio 17+27 not shown as uart). i have not found uart3 yet

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