buzhonghua Goto Github PK

apb_mstr

Generic APB master stub

e200_opensource

The Ultra-Low Power RISC Core

fpga-sm3-hash

Description of Chinese SM3 Hash algorithm with Verilog HDL

fpga_sm4

FPGA implementation of Chinese SM4 encryption algorithm.

msix-7series

Implementation of the MSI-X structure (table and PBA) in a BRAM memory. This module also offers the necessary interconnection for interact with the Xilinx 7 Series Integrated block for PCIe.

occan

Synopsys DC and Formality scripts for Opencores CAN

pulpino

An open-source microcontroller system based on RISC-V

sha256

SHA-256 implementation

sha256-1

Hardware implementation of the SHA-256 cryptographic hash function

sm4-verilog

sm4encryptor

An encrypt hardware supporting SM4 algorithm, with SCA/FI attack immunity.

systemverilog

SystemVerilog plugin for Sublime Text

testgit

testgit2

testgit_puzhh

vcs_jtag_vpi_template

A template for running jtag_vpi simulations in vcs

verilog-automatic

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

zr-soc

RISC-V SoC featuring zero-riscy core.