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Rot127 avatar Rot127 commented on June 2, 2024

This is fixed on the most recent next branch:

./cstool -d aarch64 "\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b"
 0  e1 0b 40 b9  ldr	w1, [sp, #8]
	ID: 581 (ldr)
	op_count: 2
		operands[0].type: REG = w1
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x8
		operands[1].access: READ
	Registers read: sp
	Registers modified: w1

 4  20 04 81 da  cneg	x0, x1, ne
	ID: 272 (csneg)
	Is alias: 1627 (cneg) with ALIAS operand set
	op_count: 2
		operands[0].type: REG = x0
		operands[0].access: WRITE
		operands[1].type: REG = x1
		operands[1].access: READ
	Code-condition: 1
	Registers read: nzcv x1
	Registers modified: x0

 8  20 08 02 8b  add	x0, x1, x2, lsl #2
	ID: 21 (add)
	op_count: 3
		operands[0].type: REG = x0
		operands[0].access: WRITE
		operands[1].type: REG = x1
		operands[1].access: READ
		operands[2].type: REG = x2
		operands[2].access: READ
			Shift: type = 1, value = 2
	Registers read: x1 x2
	Registers modified: x0

Especially for ARM and AArch64 I would recommend you to use it. It has way more and and correct details.
Please checkout https://github.com/capstone-engine/capstone/blob/next/docs/cs_v6_release_guide.md for details

from capstone.

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