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arbiter_rr

Round-robing VHDL arbiter

axi_lite_reg-

Registers bank with Axi-Lite interface

axi_stream_master

Source files for AXI Stream tutorial

basys3_blinker

Basys 3 simple LED blinking program (on Hardware)

basys3_magellan

Magellan - A HW monitor/debugger for Basys 3

bin_to_7seg

VHDL - Binary to seven segments decoder

chclau

Config files for my GitHub profile.

cnn_tst

repo for CNN tests

cycv_gx_hw_blink

debouncer

VHDL implementation of push-button debouncer

decoder

Generic VHDL decoder

demultiplex

Generic demultiplexer in VHDL

downcounter

VHDL code for generic downcounter

generic_reg

Generic register with load

lfsr_bit

Repository for LFSR tutorial - Random bit generation

lfsr_v1

VHDL src and testbench for LFSR tutorial

mif_gen

Matlab utility to generate .mif files for Altera memories initialization

modulo_counter

VHDL modulo counter

par2ser

pwm

PWM implementation in VHDL

saturation_counter

VHDL counter with saturation

square_waveform

VHDL square waveform generator - Code and test bench

timers

Code and testbench for the VHDL timers block tutorial (fpgasite.blogspot.com)

up_down_cnt

vhdl_arbiter

VHDL arbiter. Fixed witdh, fixed priority

vhdl_arbiter_generic

vhdl_arbiter_stat

VHDL arbiter advanced simulation

vhdl_project_master

Contains the directory tree for all VHDL projects