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4096bit-iddmm-verilog

4096bit Iterative digit-digit Montgomery Multiplication in Verilog

botan

Cryptography Toolkit

byotee-build-your-own-tees

c-verilog_ntt_rns_polymultiplier

fastecdsa

Python library for fast elliptic curve crypto

kyber

kyber-polmul-hw

Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme

kyber_fips203_python

modarithaccel

Efficient modulo arithmetic accelerator design (mod add, mod sub, mod mul, mod exp) for fixed/arbitrary prime numbers at RTL-level (VHDL/Verilog).

modexpowering3

a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier

montgomery1024

Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation

pq-riscv

A repository for analysing NIST post quantum cryptography round 2 candidates on the RISC-V ISA.

pqc-param-ntt

pqclean

Clean, portable, tested implementations of post-quantum cryptography

proteus

NTT generator

proteus_new

python-algorithm

All Algorithms implemented in Python

rsa_vhdl

RSA implementation usign Montgomery multiplication

sha256-2

Hardware implementation of the SHA-256 cryptographic hash function

sha256_hw_accelerator

SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0

vdf-fpga

A low latency modulo squaring algorithm using Montgomery multiplication, submitted to the VDF FPGA design competition, targeting AWS FPGAs. Was awarded first prize for lowest latency in alternative approaches category.