Comments (5)
That's a good point. Gating (by default) Verilog generation on tests having passed would be safer. However, I think it's an anti-pattern to go diving through test_run_dir
to find the generated Verilog. Or: that's the issue that I'm trying to address here.
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When I started using Chisel, a side effect of not having this was that it forced me to write tests to generate hardware...
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I'd also like to see generating Verilog output added to the template, since it's ultimately something that every project will need to do, and the canonical way to generate Verilog in Chisel seems to change relatively often.
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It would be really convenient to have a code that generates Verilog, as this is always a confusing aspect of Chisel and people need it.
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I proposed a PR with it : #126
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Related Issues (20)
- Add scalafmt to this template
- mill testOnly fail HOT 1
- mill compile fail
- chisel github packaging system HOT 4
- Is v3.1.1 release really the latest ? HOT 1
- Template Cleanup failing HOT 1
- Mill compile error HOT 3
- /Chisel3/Chisel/
- Include Verilator version requirements (or a reference to the version requirement in the chisel-test repo). HOT 3
- SBT test failed HOT 6
- How to run verilator HOT 4
- How to infer a parametrized top module HOT 5
- Continuous Integration HOT 1
- skeleton and sbt-chisel-dep HOT 2
- Making the repo as a github template project HOT 3
- Request for a little tutorial on how to use the template.
- Update to the latest stable chisel release HOT 1
- The GCDSpec test class comment document and the class name are inconsistent
- Show how to generate a VCD with Chiseltest
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