Comments (1)
has the link been updated but the repo hasn't moved yet?
That is the case. Nonetheless, see #305.
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Related Issues (20)
- Typedef Enum Width Default to one bit HOT 6
- Localparam not working properly HOT 4
- Signal not in Net List with one bit wires HOT 3
- Unable to handle Shift with Ternary operator HOT 6
- Array does not work with integers HOT 6
- Codebreaker Lab Failure HOT 6
- Switch to using openFPGALoader as the default tool to upload bitstreams to xc7 devices
- JTAG init failed with: unable to open ftdi device HOT 2
- What happened to the LiteX Linux and LiteX SATA demos? HOT 1
- make: f4pga: No such file or directory make: *** [Makefile:10: build] Error 127 HOT 3
- Built in gates cannot take multi-bit signal (Surelog) HOT 4
- It is very hard to find the design / example list now HOT 6
- add support for xc7a50tfgg484-1
- Update litex_demo to use F4PGA flow and current LiteX
- PicoSoC demo does not work out of the box HOT 3
- The final installation command is very easy to mess up HOT 2
- Update README files of xc7/Example-Projects to add instructions for removing the generated files produced during the build process.
- linux_litex_demo VexRiscv_Linux.v needed by arty_35/top.eblif
- btn_counter on Arty a7?
- litex_demo top.bit not found
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