Migen - Cat() simulation not matching verilog when Cat object is sliced about f4pga-examples HOT 5 CLOSED

Hi @scted,

This sounds like a Migen issue, not something that is specific to symbiflow-examples? Migen issues can be reported as https://github.com/m-labs/migen

Thanks,

Tim @mithro Ansell

GitHub

m-labs/migen

A Python toolbox for building complex digital hardware - m-labs/migen

from f4pga-examples.

almost certainly migen ... was told to report anything remotely related to the examples (using the migen installed by the examples) here but will also post on m-labs

from f4pga-examples.

@mithro FYI ... m-labs/migen#228

real issue with a workaround ... which is to assign the Cat object to an intermediate signal of equal size and then slice the intermediate signal

do you know anything about ghdl? ... "Is this any good? https://github.com/ghdl/ghdl-yosys-plugin"

m-labs think emitting vhdl would be better ... seems like verilog may be difficult and errorprone

do i close this issue here or do you? #githubrookie

GitHub

ghdl/ghdl-yosys-plugin

VHDL synthesis (based on ghdl). Contribute to ghdl/ghdl-yosys-plugin development by creating an account on GitHub.

from f4pga-examples.

Hi @scted I did some a fast check how your example behaves in nMigen. Had to tweak the code a little to be nMigen compliant:

from nmigen import *
from nmigen.back import verilog

class TestRHSCat(Elaboratable):

    def __init__(self):
        self.ins = Signal(2)
        self.outs = Signal(2)

        self.s0 = Signal()
        self.s1 = Signal()

    def elaborate(self, platform):
        m = Module()
        #Cat_object of interest
        cat_bus = Cat(self.s0, self.s1)
        m.d.comb += cat_bus.eq(self.ins)

        #using using slices of cat_bus
        m.d.comb += self.outs[0].eq(cat_bus[0])
        m.d.comb += self.outs[1].eq(cat_bus[1])

        return m

if __name__ == "__main__":
    rhscat = TestRHSCat()
    print(verilog.convert(rhscat, ports=[rhscat.ins, rhscat.outs]))

And I got the following Verilog:

/* Generated by Yosys 0.9+3667 (git sha1 e7f36d01, clang 10.0.0 -fPIC -Os) */

(* \nmigen.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "nMigen" *)
module top(outs, ins);
  (* src = "ntest.py:7" *)
  input [1:0] ins;
  (* src = "ntest.py:8" *)
  output [1:0] outs;
  (* src = "ntest.py:10" *)
  wire s0;
  (* src = "ntest.py:11" *)
  wire s1;
  assign outs[1] = s1;
  assign outs[0] = s0;
  assign { s1, s0 } = ins;
endmodule

The generated Verilog is much simpler than the one from migen. Also, it looks correct - slicing worked fine here.

from f4pga-examples.

@kgugala ... cool ... might give nMigen a try and see what i can break:) ... interesting that Yosys is generating the code.

from f4pga-examples.