Comments (1)
looks like on the sink side, there's a mux on the valid that muxes between valid and count being off
so even when valid pulse is short and not captured in some scenarios then source's count will be incremented and sink and source counts not matching will serve as a new valid alternative
from rocket-chip.
Related Issues (20)
- Running a custom binary after changing the rocket-chip configuration HOT 1
- HLV/HSV flushes pipeline HOT 1
- How to generate rocket chip in verilog HOT 4
- How to generate Boom core on other FPGA platforms like zcu102 HOT 3
- Remove Scalar Crypto HOT 4
- Embrace new world Chisel. HOT 12
- SimJTAG connecting to OpenOCD HOT 1
- How to Remove PTW from Rocket Core. HOT 2
- LR/SC unexpectedly fails when there is a jump in program HOT 1
- It is needed to clarify dependent tools version HOT 5
- Error in AXI4 Xbar with unused fields HOT 1
- Executing c.fld on Rocket chip load the wrong value in the destination register HOT 1
- Divide by zero on the Rocket chip and writes `0x0` to `rd` instead of `0xffffffffffffffff`
- REMU `x` by zero on the Rocket chip writes `0x0` to `rd` instead of `x` HOT 1
- "Hello world" simulation target and instruction in README.md
- can I remove the itim and tlb from the icache ? HOT 1
- Compile error on Chisel 6+ due to firrtl.options.RegisteredLibrary HOT 1
- Debugging with GCD Link broken
- Error in ./build.sh setp of rocket-tools HOT 1
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from rocket-chip.