Support for ready/valid about chiselverify HOT 2 OPEN

When you implement some HW that uses ready/valid handshake it would be good to test what happens on trying to push data as fast as possible. I guess this is similar to the AXI bus functional model. Yes, just the interface alone is not much that can be tested, we need an idea of the device. However, splitting the sender and the receiver into different threads will make this easier. Not sure if this is clear writing on my side.

Another try: what about testing this FIFO thing with our framework: https://github.com/freechipsproject/ip-contributions/tree/master/src/main/scala/chisel/lib/fifo ? It would need two threads: one writing and one reading with some coordination.

from chiselverify.

I'm not entirely sure what you mean by adding support for them. Aren't ready/valid signals simply considered as regular ports? What exactly is missing that we would need to add to support this?

from chiselverify.