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kknox avatar kknox commented on August 26, 2024

I'll try this out tomorrow when I am at work; I had holiday today. The only references to CL_MAP_WRITE_INVALIDATE_REGION are in coo2csr; is that what you are executing? I don't understand why that would fail; are you testing on an nvidia platform maybe? Looks like that flag was added in cl1.2. It's use is exactly like CL_MAP_WRITE, except that it can be faster. Also, I only write that memory, I never read from it, so the problem has to come from the memory not being unmapped correctly.

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jpola avatar jpola commented on August 26, 2024

Yes it is that code. I did not study the code deeply but originally your code is mapping the same buffer for reading and writing.

clMemRAII< cl_float > rCooValues( control->queue( ), pCooMatx->values );
...
cl_float* fCooValues = rCooValues.clMapMem( CL_TRUE, CL_MAP_READ, pCooMatx->valOffset( ), pCooMatx->nnz );
...
cl_float* fCsrValues = rCooValues.clMapMem( CL_TRUE, CL_MAP_WRITE_INVALIDATE_REGION, pCsrMatx->valOffset( ), pCsrMatx->nnz );

Similarly you are mapping coo colindices into iCooColIndices (for reading) and iCsrColIndices for wiriting. Indeed the difference between csr and coo matrix lays in the rows but for me that code is making the troubles. At least it is working when i change to the state which I think is correct:

cl_float* fCooValues = rCooValues.clMapMem( CL_TRUE, CL_MAP_READ, pCooMatx->valOffset( ), pCooMatx->nnz );
cl_int* iCooColIndices = rCooColIndices.clMapMem( CL_TRUE, CL_MAP_READ, pCooMatx->colIndOffset( ), pCooMatx->nnz );
cl_int* iCooRowIndices = rCooRowIndices.clMapMem( CL_TRUE, CL_MAP_READ, pCooMatx->rowOffOffset( ), pCooMatx->nnz );

cl_float* fCsrValues = rCsrValues.clMapMem( CL_TRUE, CL_MAP_WRITE, pCsrMatx->valOffset( ), pCsrMatx->nnz );
cl_int* iCsrColIndices = rCsrColIndices.clMapMem( CL_TRUE, pCsrMatx, pCsrMatx->colIndOffset( ), pCsrMatx->nnz );
cl_int* iCsrRowOffsets = rCsrRowOffsets.clMapMem( CL_TRUE, CL_MAP_WRITE, pCsrMatx->rowOffOffset( ), pCsrMatx->m + 1 );

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kknox avatar kknox commented on August 26, 2024

This was fixed in PR #44

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