How to check the signal value inside a for loop about cocotb HOT 7 CLOSED

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Hey guys, sorry to intrude on firemountain issue , just to add that I see the same issue albeit on a more convoluted fashion but it boils down to the same. I am using 1.7.2 cocotb, using VCS: VCS Release version S-2021.09-SP2-1_Full64 and here is a snippet:

genvar stream_group_gen;
genvar stream_gen;

for (stream_group_gen = 0; stream_group_gen < 8; stream_group_gen++) begin: overlay_stream_group

for (stream_gen = 0; stream_gen < 8; stream_gen++) begin: overlay_stream

stream_module stream_inst()

end
end

When I try to access this via : dut.overlay_stream_group[0].overlay_stream[0].stream_inst

I get the same error as the OP, a print(dir(dut)) gives no member named overlay_stream_group, but weirdly we get a member named stream_inst. which is not an array so any access to it while it does not complain at runtime, goes to nowhere

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@genfrontier See #2187. It seems that VCS doesn't have great support for discovering generate loops, but there is a work-around.

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Thanks ktbarret, i was able to bypass this by using :

fullsig = dut._id(f"overlay_stream_group[{groupsel:d}].overlay_stream[{streamsel:d}].stream_inst", extended=False)

The trick is to use as the ._id string the whole hierarchy from the first generate loop onward. Leaving it here as might someone find it helpful

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may I have a elaborate explanation on what the mean of simulator I use, I guess it's verilator? and I just built it with python3, I still have this problem, so how u grab this signal if it's defined like that.

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Verilator is a simulator. What version of verilator? You can find out by running verilator --version.

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