COCOTB + Verilator reads stale signal values when on clock posedge about cocotb HOT 1 CLOSED

This is how normal simulators and HDLs works. When you sensitize yourself to a value change on a signal, the process awakens after the value changes, but before any of the other sympathetic signals are updated (giving you the chance to add your own non-blocking writes for the next delta cycle).

If you want to read the signals after they have all "settled" you can use await ReadOnly() to put yourself in the postponed region. You won't be able to do any writes at this point. The other solution is to change your code to work more like HDL by sampling the last cycles settled values at the next clock edge.

from cocotb.