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aes-processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amy_mcu

A MCU implementation based PODES-M0O

arm_m3_design

personal practice

awesome-dv

Awesome ASIC design verification

b0911009y-computer-architecture-lab

bag_framework-1

Berkeley Analog Generator

bag_framework2

Berkeley Analog Generator

c8051f

C8051F Mcu example source

cocoon

An infrastructure for integrated EDA

core-v-mcu-uvm

CORE-V MCU UVM Environment and Test Bench

cortexm0_soc

cortexm0_soc-1

Cortex M0 based SoC

cpplinks

A categorized list of C++ resources.

craft2-chip

Craft 2 top-level repository

dsi-shield

Arduino MIPI DSI Shield

dsp

CompArch Final Project: DSP Architecture

e200_opensource

The Ultra-Low Power RISC Core

e203_hbirdv2

The Ultra-Low Power RISC-V Core

efpga---rtl-to-gds-with-sky130

This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk

fast

FAST

fpu

synthesiseable ieee 754 floating point library in verilog

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

h265-encoder-rtl

hdlgen

hello-world

Just another repository

ic_flow_platform

IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow contral.

learn-algorithms

算法学习笔记

logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

mipsfpga-plus

MIPSfpga+ allows loading programs via UART and has a switchable clock