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device-tree-xlnx

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

dvb_fpga

RTL implementation of components for DVB-S2

embeddedsw

Xilinx Embedded Software (embeddedsw) Development

fpga_cores

gitguide

git tutorial

hdl

HDL libraries and projects

hdl_string_format

VHDL package to provide C-like string formatting

openmct

A web based mission control framework.

polarfire-eval-kit

PolarFire-Eval-Kit

satcat5

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

sphinx_rtd_theme

Sphinx theme for readthedocs.org

spyder-docs

Documentation for Spyder, the Scientific Python Development Environment

symbolator

HDL symbol generator

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module

vhdl-jesd204b

JESD204b modules in VHDL

vhdl-style-guide

Style guide enforcement for VHDL

vitis_accel_examples

Vitis_Accel_Examples

vitis_libraries

Vitis Libraries

vivado-design-tutorials

vmk180-trd

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

wb2axip

Bus bridges and other odds and ends