Comments (1)
CalMacCQ
commented on July 22, 2024
In this particular example I think the difference in 2 qubit gate count (pre rebase) is due to the fact that Aer can run CU1 gates natively. The heavier optimisations that go via CX have more 2q gates.
These CU1 gates require 2 CX gates each to implement in general so the heavier optimisation which goes via {TK1, CX} has more two qubit gates in the resulting circuit.
This maybe isn't so surprising in this case. The gateset for AerBackend is very broad and not very representative of a real device.
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