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16-bit-unsigned-divider

adders

arrange-collections-for-your-account-in-zhihu.com

My first complete script in python. Since zhihu.com is poor in its collection function, I'm thinking maybe combining all the answers in one webpage would be easy for search.

crc

Be very very careful when trying to use the content of my code into you lab assignment in any vlsi course. Professor is very very strict in plagiarism. It detects easily with their tools and the punishment is very severe.

ddr2_controller

dff

doubanhouseleasing

fifos

flaskonheroku

Fan cafe member Statistics

getpicfromtistory

huxblog-boilerplate

Boilerplate of Hux Blog

jkflipflop

layout-router-design

2D maze router design code in verilog

leetcode

My LeetCode C++ Solutions

leetcode-py

And they say Python is slow...

microprocessor

Full custom design of a general purpose Multi-Cycle Microprocessor, consisting of SRAM, ALU and Register Files, supporting 13 different instructions including memory instructions like LOAD STORE, logic instructions like AND OR XOR, ADD instructions with 3 different burst lengths and 16-bit division instruction. Optimized in terms of area, delay and power consumption. Perl script used for decoding instructions, generating input control signals and result verification.

perl_syntax

photopreserve-analysis

python-memo

sram_part1

sram_part2

superscalar

systemc-study

verilog-and-design-compiler

wxpython

Read-only mirror of the wxPython SVN repo (automatically updated). Report issues here: http://trac.wxwidgets.org/