Comments (1)
Yes, it is necessary to do this yourself. Many ECC chips will handle it for you in hardware. If you need a software implementation, there's example code provided for BCH and Hamming codes.
Whichever way you do it, remember to read enough data during a partial read to get a complete ECC block -- partial reads require ECC too.
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Related Issues (20)
- Very aggressive garbage collection --- a configuration problem? HOT 6
- Performance Tuning HOT 8
- journal.c: cp_free does an illegal dhara_nand_is_free if on last group and none of the pages are free HOT 6
- DHARA+FATFS: boot sector is remapped without a copy HOT 12
- When the bad block appears in the read ECC error, dhara cannot be processed HOT 4
- example HOT 1
- Using a different GC ratio with an existing flash map HOT 2
- Garbage Collection Instrumentation HOT 2
- Using dhara for nor and nand flash - some questions HOT 5
- Using Dhara in Zephyr HOT 10
- Map Sync Time HOT 6
- `dhara_journal_enqueue` can fail with `DHARA_E_NONE` HOT 1
- `try_delete` sets an alt pointer twice
- dhara_map_capacity returns inconsistent values HOT 4
- How to generate LLR for soft LDPC decoder in nand flash via multiple reads?
- gc fails if checkpoint page is corrupted
- Expected overheads / available capacity HOT 5
- user error: (Was: Multi-plane NAND support)
- I'm taking this code as reference for my flash MT29F4G01ABAFDWB
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