Comments (2)
Hi @axiomlegend Thanks for the suggestion
One of the things we try to do with Embench is to leave the programs as we find them as far as is possible. The only changes we make are to ensure they work on a range of architectures from 8-bit to 64-bit and occasionally to fix bugs that mean they won't work. TBH the biggest change is usually fixing assumptions about the size of value that can fit in an int
. On some small architectures, int
is only 16-bits long.
The programs are far from perfect, but that is deliberate. The last thing we want is a set of programs rewritten to what we believe the perfect solution would be, since that doesn't reflect the real world.
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Marking as closed.
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Related Issues (20)
- Failed to compute speed benchmarks for riscv
- Unable to run benchmark-speed HOT 1
- Does Embench support RISCV64 ISA HOT 1
- In nbody some toolchains hoisting bodies_energy out of main loop HOT 5
- In the st benchmark some toolchains hoisting/removing the computation from the benchmarking loop HOT 4
- crc32 size increases is we specify a frequency with --cpu-mhz different from 1 MHz
- nettle-sha256 does not work with CFI that enforces types HOT 2
- Discussing potential advantages of unaligned access and bi-endian hardware support HOT 2
- Remove I/O dependencies of md5sum benchmark
- How to run embench on qemu for RISC-V?
- Tarfind isn't portable due to assuming struct layout HOT 3
- EMB2.0: Automatic stdlib size overhead adjustment HOT 6
- EMB2.0: Update python build scripts HOT 1
- OpenRISC Port Issue #1: Inconsistency in size benchmark success reporting HOT 1
- OpenRISC port Issue #2: Inconsistency in reporting size results HOT 1
- OpenRISC port Issue #3: Binary header issue with -nostdlib/-nostartfiles flags HOT 1
- OpenRISC port Issue #4: Conflicting .so definitions in dummy libs and OpenRISC toolchain libc HOT 1
- Embench 2.0: Missing Depthconv benchmark's reference platform baseline data.
- Broken fix to tarfind from #138
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