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ailearning

AiLearning: 机器学习 - MachineLearning - ML、深度学习 - DeepLearning - DL、自然语言处理 NLP

chiselverify

codeparkshare

Python初学者（零基础学习Python、Python入门）书籍、视频、资料、社区推荐

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

cplusplusthings

C++那些事

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

e200_opensource

The Ultra-Low Power RISC Core

example_uvm

UVM实战随书源码

hw

RTL, Cmodel, and testbench for NVDLA

ic_verification_script

some script for IC verification

leetcode

Python & JAVA Solutions for Leetcode

memory

model_example

Simple SystemC/TLM2 model example

nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

oh

Verilog library for ASIC and FPGA designers

openc910_modified

opentitan

OpenTitan: Open source silicon root of trust

openwifi

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

pipeline

A 5 stage pipeline simulator

regmodel

This script builds the UVM register model, based on pre-defined address map in markdown (mk) style

risc-v-tlm

RISC-V SystemC-TLM simulator

riscv-simulator

A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation

riscv-simulator-1

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

systemc-examples

A repository for SystemC Learning examples

systemverilogassertions

Examples and reference for System Verilog Assertions

systemverilogreference

training labs and examples

tlm-2.0

Getting started with TLM-2.0 from https://www.doulos.com/knowhow/systemc/tlm2/#anchor1

tlm2-gtestbench

SystemC TLM2 testbench using gtest framework.

uvm_axi

uvm AXI BFM(bus functional model)