How are verilog modules implemented in icestudio? about icestudio HOT 4 CLOSED

Are Varilog variable names local to modules? In a code block with multiple modules?

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Is there a log file or output file that the "builder" or "uploader" creates that has details about build errors?
Some error message pop-ups aren't very detailed, so I'm hoping to find details about the error.

Also, sometimes when I press "upload", it works for a few seconds and finishes without error messages, but the design is not uploaded to the board. How can I find out why?

Thanks!

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Hi @ssjimh ! each icestudio block is a verilog module, but you could try to define a module inside the block (the scope should works only into this code block).

For the moment you could import verilog files that are in your project folder. For the moment folders are not supported (but very soon support it, i'm working on it!).
For this, you only put a comment at the start of the verilog editor:

// @include ram_sdp.v

ram_sdp.v for example should be in the same folder that your .ice

About the yosys output, you could find in this option:

Greetings!

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Thanks Cavearr!

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