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aes-fpga

AES加密解密算法的Verilog实现

aes-riscv

Ways to accelerate AES in a RISC-like CPU pipeline.

aes-verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

aes_ip

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

amd_aecg_summer_school_projects

Xilinx暑期学校

ascon-verilog

Verilog Hardware Design of Ascon v1.2

cdma_accelerator

这个不错，学完CDMA可以再做个这个

easy_axi

Learn the basics of AXI against the code and protocol

fpga-can

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

fpga-gzip-compressor

FPGA-based GZIP (deflate) compressor. Input raw data and output standard GZIP format (as known as .gz file format). 基于 FPGA 的流式 GZIP 压缩器。输入原始数据，输出标准的 GZIP 格式，即常见的 .gz / .tar.gz 文件的格式。

fpga-jpeg-ls-encoder

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图象压缩。

fpga-mpeg2-encoder

FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。

graduation-proj

硕士毕设工作文件夹

ic_fpga

数字IC相关资料

ip_rtl

Some simple IP.

moyu

Github 摸鱼大全！

piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

point-cloud-materials

点·云团队资料库

sha-256

ucsd ece111 project3

sm3_core

sm4-fpga

SM4 is a block encryption algorithm

tiny-aes-c

Small portable AES128/192/256 in C

ustc-rvsoc

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

web_test

xray-script

Xray：（VLESS/VMess）-（TCP/gRPC/WebSocket）-（XTLS/TLS）+Web 搭建/管理脚本

zju-icicles

浙江大学课程攻略共享计划