Question about optional reset module about chisel-bootcamp HOT 4 CLOSED

class DelayBy1(resetValue: Option[UInt] = None) extends Module {
    val io = IO(new Bundle {
        val in  = Input( UInt(16.W))
        val out = Output(UInt(16.W))
    })
    val reg = if (resetValue.isDefined) { // resetValue = Some(number)
        RegInit(resetValue.get)
    } else { //resetValue = None
        Reg(UInt())
    }
    reg := io.in
    io.out := reg
}

println(getVerilog(new DelayBy1))
println(getVerilog(new DelayBy1(Some(3.U))))

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This is the original code.

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What you are describing is the desired behavior.

Registers without resets are synthesizable. As you say, it may introduce bugs if the garbage initial value is used in some undesirable way, but in some situations registers without reset values may be OK.

In the case of this module, imagine that there is a block that reads the value of io.out, but only does so several cycles after io.in is valid data (perhaps io.in is valid 2 cycles after reset and io.out is read 3 cycles after reset).

Resets can add extra overhead, especially because chisel resets are synchronous.

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@grebe Thank you for your explanation!

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