VCS backend fails on blocks with no IOs (standalone) about chisel-testers HOT 4 OPEN

Is this actually legal according to the Verilog spec--i.e., is VCS wrong, or is Verilator too lax?

from chisel-testers.

I don't see any trailing commas allowed in the Verilog 2001 module instantiation spec, unless the thing called "expression" is allowed to be empty. But if it was, then there would be three parameters to module and they are only two where to module is defined.

Fixing this should be easy---it is not as if verilator is going to fail if we remove the extra comma.

from chisel-testers.

Yeah, of course. I asked because I was going to file a ticket if it was a VCS bug.

from chisel-testers.

I think it's because verilator and FIRRTL tests don't generate a Verilog test harness. Only VCS does.

from chisel-testers.