Comments (2)
NOTICE: DUE TO PERSONNEL CHANGES AT GOOGLE, THIS PROJECT IS NOT CURRENTLY MAINTAINED.
Hi @SHIBSIE , you have done nothing wrong. It has to do with the fact that the Basys3 board has no extra external memory (in comparison, Digilent's Arty board has a large external memory). As a consequence, the Litex-boards target file for Basys3 doesn't declare a "main_ram"
memory region. This is what causes the error that you see.
Aside: This used to be the case also for the Kosagi Fomu board. It has a large (128kB) on-FPGA RAM, but it used to be a single sram
region. We handled that by modifying the linker script to put all of the sections that typically go into main_ram
into sram
. (When Litex-boards made a change that split the 128kB into 64kB sram
and 64kB main_ram
, we had to do another hack to shift all of the memory back into the sram
region: https://github.com/google/CFU-Playground/blob/main/soc/board_specific_workflows/ice40up5k.py#L74-L77).
Back to the Basys3. I guess we never attempted putting CFU Playground on it. The first question is, can we build an on-FPGA RAM large enough for our needs. For the no-tflm project, I would guess that the answer is yes. Then, we'd need to make a custom linker.ld script for the basys3.
I think I remember (this was a long time ago when I looked at it) that on Basys3, the FPGA could not access the flash -- the flash could only be used to hold the bitstream to configure the FPGA, but not as extra storage that the FPGA could access. This is unfortunate since it means we need to put even code and read-only data into our limited on-FPGA RAM. I think that is why I gave up on trying to use Basys3.
I'll try to find time to dig out my Basys3 board in the next few days, but I cannot promise anything.
from cfu-playground.
Hello, Thank you for your quick response. I get what the problem is, I was just using the basys3 board becuase I had it on hand and wanted to test out if everything was working fine, but for my project I will be using a bigger board.
Do you have any idea if the ZedBoard would work alright? Thank you for your response and time.
from cfu-playground.
Related Issues (20)
- "make load" step got stuck HOT 5
- OSError: Failed to find config file
- How to use renode for other LiteX boards? HOT 1
- "make renode" is broken -- due to Verilator 5.006? HOT 3
- get stuck when load software.bin through /dev/ttyUSB1 HOT 8
- Need help with understanding software part of mnv2 example HOT 1
- How to accelerate `make prog` run time HOT 1
- Use of L2 in FPGA setups HOT 1
- Using BRAMs instead of LUTRAMs for big cfu storage HOT 1
- error:Could not locate Gemfile HOT 2
- Issue in synthesis for large design HOT 2
- Synthesizing the model
- `make load` on a Kosagi FOMU board HOT 4
- How to print the "perf counters" when I use the FPU variant? HOT 1
- Failing CI for Lattice Nexus / prjoxide tests
- Failing CI for Symbiflow installation -- out of disk space
- Renode Error HOT 4
- Symbiflow not working for Xilinx HOT 6
- /dev/ttyUSB0 hangs during load HOT 6
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