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alu

ALU

always_comb

In an always block which is used to model combinational logic, forgetting an else leads to an unintended latch. To avoid this mistake, SystemVerilog adds specialized always_comb and always_latch blocks, which indicate design intent to simulation, synthesis and formal verification tools. SystemVerilog also adds an always_ff block to indicate sequential logic.

apb_uvm

comparator

Binary comparators, also called digital comparators or logic comparators, are combinational logic circuits that are used for testing whether the value represented by one binary word is greater than, less than, or equal to the value represented by another binary word. Two basic types of comparator can be used.

counter

counter

d-flip-flop

The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the reset through an inverter.

data-types

Enumeration

enumeration-datatypes

Enumeration is a useful way of defining abstract variables.

example-coding

Example 1

example-ovm

example-uvm

file-i-o-system-verilog

In order to use the tasks $fdisplay, $fmonitor etc., you must first open a file using the system function $fopen. $fopen requires a file name and a mode. To open a file for writing, the mode is "w". $fopen returns an integer value – file descriptor – or 0 if the file could not be opened. This may happen if, for example, the disk is full, or there is no privilege to write to the specified file. It is a good idea to check the value returned by $fopen. The file descriptor is then used as the first argument when calling $fdisplay, $fmonitor etc. The other arguments are exactly the same as for the corresponding tasks ($display, $monitor etc.) When you have finished writing to the file, you can close the file with the system task $fclose. Files that are not closed with this system task are automatically closed when simulation finishes

fork-join

A Verilog fork...join block always causes the process executing the fork statement to block until the termination of all forked processes. With the addition of the join_any and join_none keywords, SystemVerilog provides three choices for specifying when the parent (forking) process resumes execution.

fsm

FSM

full-adder

Verilog Design and Testbench

hello-world

Just another repository

jelly_bean-uvm

This post I will write a simple tutorial on verification methodology for Jelly_bean. This example I took form this link

memory-model

multiplexer

Multiplexer also know as Mux is a device that selects between several analog or digital input signals and forwards it to a single output line. A multiplexer of inputs has select lines, which are used to select which input line to send to the output.

mux

multiplexer is a device that selects between several analog or digital input signals and forwards it to a single output line. A multiplexer of inputs has select lines, which are used to select which input line to send to the output.

oop-object-oriented-programming-for-system-verilog

n system verilog all the properties of the class are public by default or we can say it be accessed outside the class directly using the dot operator. If we want to protect the access of the class variables/properties from outside the class we can use the local keyword. Hiding the properties from being accessed outside the class is called encapsulation. If we want to make the properties accessible in the extended classes but not outside the classes. We can declare the properties as protected. Then it will be available in the extended classes but not in the main program.

overloading-and-overriding

port-switch

priority-encoder

This is encoder

randomization

Verilog Constraint Random Verification

system-verilog-example

Example code for string declaration

system-verilog-verification-environment

t-flip-flop

The clock has to be high for the inputs to get active. Thus, T flip-flop is a controlled Bi-stable latch where the clock signal is the control signal. Thus, the output has two stable states based on the inputs which have been discussed below. The T flip flop is the modified form of JK flip flop.

task-and-function

Supporting system for systemverilog are tasks and functions

template-