Comments (5)
I'm sorry for slow response, I nothiced this issue today.
At first, assign large maxSize to the constructor of CodeGenerator.
I write the following code to avoid many instance of CodeGenerator.
Does this way solve your problem?
void *func1;
void *func2;
void *func3;
...
CodeGenerator()
{
#if 1
func1 = getCurr();
genFunc1();
align(16);
func2 = getCurr();
genFunc2();
align(16);
func3 = getCurr();
genFunc3();
#else
// when using AutoGrow
const size_t func1Offset = getSize(); // always 0
genFunc1();
align(16);
genFunc2();
const size_t func2Offset = getSize();
align(16);
genFunc3();
const size_t func3Offset = getSize();
...
func1 = getCode() + func1Offset;
func2 = getCode() + func2Offset;
func3 = getCode() + func3Offset;
#endif
}
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I avoided creating instances of CodeGenerator on the fly, just create some during program initialization, long initialization time isn't a problem in my case. The solution above might help, but not exactly what I want. Here is my problem:
I'm implementing something like a mini-SQL interpreter. Instead of interpreting everything, I want to use a JIT compiler/assembler to compile some SQL queries into machine code. So I need to generate and destroy unlimited number of functions. A light-weight JIT compiler/assembler is very important to my program.
If the solution above is used, I probably would generate and destroy functions in batches, for example, after generating 1k functions, destroy them all, then create another CodeGenerator instance. But cache problems might come into my way (just my guess, not sure): data cache miss, stale instruction cache etc.
Currently most queries are interpreted by my program, only very little functionality is implemented in JIT.
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Though I can't guess the cost of penalty of instruction cache miss, I try to add reset() method to CodeGenerator to reuse the instance at develop branch.
458a6e0
If this runs well, then I'll merge it into master branch.
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It's not just about performance.
On ARM CPUs, self-modifying applications have to invalidate instruction cache deliberately. I'm not sure about Intel/AMD CPUs. When multi-core systems, multi-threaded applications, old CPU architectures and all other things come together, things may get nasty.
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Of couse, it is bad to modify the region of code where CPU is running.
But Intel Processor supports Self-modifying code, so I think the problem is only about performance. I think we can get benefit if the generated functions are called many many times.
Intel optimization manual 3.6.9.1 Self-modifying code.
Self-modifying code (SMC) that ran correctly on Pentium III processors and prior
implementations will run correctly on subsequent implementations.
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Related Issues (20)
- array-bounds error HOT 10
- Broken test suite on x86 (IA-32) HOT 2
- WAITPKG HOT 2
- Build failure with XBYAK_NO_EXCEPTION HOT 2
- Cpu::has() check is inconsistent HOT 3
- The version number went backwards: 6.052 -> 6.06 HOT 10
- Compilation issue with template trick on MSVC HOT 3
- Standalone CPUID flags are coupled with `AVX512F` HOT 1
- movzx eax, ah HOT 3
- "invalid token at start of a preprocessor expression" HOT 5
- Question on error stickyness HOT 3
- Error raised when using vpmovsdb with memory mask HOT 4
- x32 support HOT 11
- Please use ${CXX} instead of hardcoding g++ because in different systems C++ compiler has different executable names HOT 2
- RISC-V ISA support HOT 2
- aligned allocation requests should be rounded up to page size HOT 2
- AMD MONITORX instructions support HOT 2
- Support for Intel APX and AVX10 HOT 4
- Support for xbegin, xend, xabort functions HOT 1
- APX support in progress HOT 6
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