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32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

aimet

AIMET is a library that provides advanced quantization and compression techniques for trained neural network models.

altera-cyclone-iv-board-v3.0

Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board

asic_labs_fa21

awesome-hust-cs-mips-cpu

HUST CS 19级组原课设/华中科技大学计算机组成原理课程设计/MIPS五段流水CPU/华中科技大学计算机组成原理课程设计/华科组原课设/MIPS-CPU/单周期/流水线/分支预测。来自学长的溺爱x，让你copy的明白。

awesome-model-quantization

A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo.

basic_verilog

Must-have verilog systemverilog modules

bitpack

BitPack is a practical tool to efficiently save ultra-low precision/mixed-precision quantized models.

bsq

BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)

cyclonevsoc-examples

Examples using the Cyclone V SoC chip

deep-learning-for-image-processing

deep learning for image processing including classification and object-detection etc.

deeplearningsystem

Deep Learning System core principles introduction.

distiller

Neural Network Distiller by Intel AI Lab: a Python package for neural network compression research. https://intellabs.github.io/distiller

dsp48e1-fp

Project aimed at implementing floating point operators using the DSP48E1 slice.

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

examples

A set of examples around MegEngine

fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga_labs_fa21

FPGA Labs for EECS 151/251A (Fall 2021)

fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado

gemmini

Berkeley's Spatial Array Generator

gmpq

This is the pytorch implementation for the paper: Generalizable Mixed-Precision Quantization via Attribution Rank Preservation, which is accepted to ICCV2021.

gptq-for-llama

4 bits quantization of LLaMa using GPTQ

haq

[CVPR 2019, Oral] HAQ: Hardware-Aware Automated Quantization with Mixed Precision

hawq

Quantization library for PyTorch. Support low-precision and mixed-precision quantization, with hardware implementation through TVM.

how-to-write-makefile

跟我一起写Makefile重制版

imagenet

This implements training of popular model architectures, such as AlexNet, ResNet and VGG on the ImageNet dataset(Now we supported alexnet, vgg, resnet, squeezenet, densenet)

int_fp_mac

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

ippro

The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.

limpq

Official implementation for paper "Mixed-Precision Neural Network Quantization via Learned Layer-wise Importance"