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hungtaowu's Projects

coremark icon coremark

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

e200_opensource icon e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

gmssl icon gmssl

支持国密SM2/SM3/SM4/SM9/ZUC/SSL的OpenSSL分支

jtag_dpi icon jtag_dpi

JTAG DPI module for SystemVerilog RTL simulations

open_regmodel icon open_regmodel

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

peakrdl icon peakrdl

SystemRDL command-line control/status register compiler toolchain

peakrdl-html icon peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-regblock icon peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl-uvm icon peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

verilog_spi icon verilog_spi

A simple Verilog SPI master / slave implementation featuring all 4 modes.

wujian100_open icon wujian100_open

IC design and development should be faster,simpler and more reliable

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