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asym_bft

Asymmetry in Butterfly Fat Tree FPGA NoC (FPT 2023)

bert

Bitstream Embedded RAM Transfusion

doblink

edalize

An abstraction library for interfacing EDA tools

ese532_code

ese532_handouts

Course handouts for ESE532 at UPenn

estream4fccm2021

fpga-tool-perf

FPGA tool performance profiling

hipr

huffmanvivadoproject

huffmanVivadoProject submodule for bert

hydra

Hydra is a framework for elegantly configuring complex applications

nesteddfx

This is repo to show how to use nested DFX on ZCU102 board

old_systolic_placer

Updated systolic placer

pld2022

prflow_nested_dfx

Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)

prflow_refine

REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs (FPGA 2024)

prjxray

Documenting the Xilinx 7-series bit-stream format.

pythondata-cpu-vexriscv-stream

Python module containing verilog files for vexriscv cpu (for use with LiteX).

rosetta

Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

rosetta_vitis

slurm-gcp

Slurm on Google Cloud Platform

symbiflow-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research