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alchitry-verilog-exercises

Sequence of exercises used to learn Verilog on Alchitry Au FPGA

beneater-8bit-computer

Implementation of Ben Eater's design for an 8 bit breadboard computer

dvb_capture

Exercise in processing Transport Stream broadcast over DVB-T

formalmethods-zipcpu-class-verilog

Verilog Examples and exercises from ZipCPU's formal methods class

gtestverilog

Extension to GoogleTest for working with Verilog designs

icebreaker-verilog

Working with IceBreaker FPGA on MacOS

nandland-verilog-exercises

Verilog Go Board Exercises from https://www.nandland.com/goboard/index.html

opencv-project1

Short Project with opencv & Face Detection

picamera

A pure Python interface to the Raspberry Pi camera module

pipelined-cpu

Experimenting with writing a 5 stage pipelined CPU in verilog

profile

C++ Intrusive Function Profiling Library

profile-visualiser

Visualise Function Profiler Logs

rules_verilator

Bazel build rules for Verilator

sock-puppets

spaceinvaders8080

Software Emulation of Intel 8080 CPU for Taito Space Invaders Arcade Game

spike-discordbot

Spiking a basic discord bot

spike-midi-input-interface

Experiment in building a midi input circuit

spike-pixelgameengine

Quick spike with OlcPixelGameEngine for HackHorsham 11th Jan 2020

spike-python-opencv

Series of short spikes of OpenCV features for the purpose of revising python OpenCV API.

spike-uart

Experiment in reading/sending UART serial comms

spike-verilator-fpga

Initial experiments in using 'verilator' to generate C++ simulations of Verilog designs

tinyfpga-verilog-exercises

Learning Verilog programming with TinyFPGA-Bx

verilog-nes

Building a Nintendo Entertainment System in Verilog

verilog-spi

Unit Tested implementation of SPI protocol in verilog

vivado-cpu6502-debugger

Replica of 6502 CPU running in a debugger framework on Vivado/ARTY-A7

vivado-nes-debugger

Vivado project for debugging NES design